MK2049-36 Datasheet CLOCK PLL

Manufacturer: Renesas

Datasheet Details

The MK2049-36 is a Phased Locked Loop (PLL) based clock synthesizer that accepts multiple input frequencies.

With an 8 kHz clock input as a reference, the MK2049-36 generates T1, E1, T3, E3, OC3 and other communications frequencies.

This allows for the generation of clocks frequency-locked to an 8 kHz backplane clock, simplifying clock synchronization in communications systems.

3.3 VOLT COMMUNICATIONS CLOCK PLL DATASHEET MK2049-36.

Packaged in 20 pin SOIC.
Pb (lead) free package.
3.3 V + 5% operation.
Meets the TR62411, ETS300 011, and GR-1244 specification for MTIE, Pull-in/Hold-in Range, Phase Transients, and Jitter Generation for Stratum 3, 4, and 4E.
Accepts multiple inputs: 8 kHz backplane clock or 10 to 50 MHz.
Locks to 8 kHz + 100 ppm (External mode).
Buffer Mode allows jitter attenuation of 10 - 50 MHz input and x1/x0.5 or x1/x2 outputs.
Exact.

Brand Logo	Part Number	Description	Manufacturer
	MK2049-36	3.3 V Communications Clock PLL	Integrated Circuit Systems

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