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MK2049-36 Datasheet

Manufacturer: Renesas
MK2049-36 datasheet preview

Datasheet Details

Part number MK2049-36
Datasheet MK2049-36-Renesas.pdf
File Size 215.82 KB
Manufacturer Renesas
Description CLOCK PLL
MK2049-36 page 2 MK2049-36 page 3

MK2049-36 Overview

The MK2049-36 is a Phased Locked Loop (PLL) based clock synthesizer that accepts multiple input frequencies. With an 8 kHz clock input as a reference, the MK2049-36 generates T1, E1, T3, E3, OC3 and other munications frequencies. This allows for the generation of clocks frequency-locked to an 8 kHz backplane clock, simplifying clock synchronization in munications systems.

MK2049-36 Key Features

  • Packaged in 20 pin SOIC
  • Pb (lead) free package
  • 3.3 V + 5% operation
  • Meets the TR62411, ETS300 011, and GR-1244
  • Locks to 8 kHz + 100 ppm (External mode)
  • Buffer Mode allows jitter attenuation of 10
  • 50 MHz input
  • Exact internal ratios enable zero ppm error
  • Output clock rates include T1, E1, T3, E3, and OC3
  • See also the MK2049-34 and MK2049-45

MK2049-36 from other manufacturers

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Brand Logo Part Number Description Other Manufacturers
Integrated Circuit Systems Logo MK2049-36 3.3 V Communications Clock PLL Integrated Circuit Systems
Renesas logo - Manufacturer

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