M306K9F8LRP Datasheet | Renesas

Description REJ03B0041-0100Z Rev.1.00 Description The M16C/6K9 group of single-chip microputers are built using the high-performance silicon gate CMOS process using a M16C/60 Series CPU core and are packaged in a 144-pin plastic molded QFP. These single-chip microputers operate using sophisticated instructions featuring a high level of instruction efficiency. To municate with host CPU, the LPC bus interface is built in. In this way, this MCU can work as slave controller in the personal puter system. The specification is target oriented specification for the development of M16C/6K9. Features - Memory capacity ROM (See Figure AA-4 ROM Expansion) RAM 3K to 5K bytes - The Min. time of instruction execution ... 62.5ns (f(XIN)=16MHz, with 0 wait, Vcc=3.3V) - Supply voltage 3.0 to 3.6V (f(XIN)=8MHZ with 0 wait) - Supply voltage for Program/Erase 3.0 to 3.6V (CPU reprogram mode, f(XIN)=16MHZ with 1 wait) - Low power consumption 52.8m W ( f(XIN)=16MHZ, with 0 wait, VCC = 3.3V) - Interrupts 38 internal and 16 external interrupt sources, 4 software interrupt sources; 7 levels (including key input interrupt) - Key input interrupts 2 (8 inputs shared with1 interrupt request X 1; 8 inputs (with event latch) shared with1 interrupt request X 1) - Multifunction 16-bit timer 5 output timers + 6 input timers - Serial I/O 5 channels (3 for UART or clock synchronous, 2 for clock synchronous) - DMAC 2 channels - Host interface LPC bus interface X 4 - A-D converter 10 bits X 8 channels (Expandable up to 10 channels) - D-A converter 8...