Description
7
Pinout 8
Typical Performance Curve 9
Functional Description 12 Reset 12 Voltage Reference 12 Analog Input 12 Clock Input 13 Jitter 13 Digital Outputs 14
Equivalent Circuits 14
Layout Considerations 15 Split Ground and Power Planes 15 Clock Input Considerations 15 By
Features
- include an over-range indicator and a selectable divide-by-2 input clock divider. The KAD2710C is one member of a pin-compatible family offering 8 and 10-bit ADCs with sample rates from 105 to 350MSPS and LVDS-compatible or LVCMOS outputs (Table 1). This family of products is available in 68-pin RoHS-compliant QFN packages with exposed paddle. Performance is specified over the full industrial temperature range (-40°C to +85°C). AVDD2 AVDD3 CLKDIV OVDD
CLK_P CLK_N
Clock Generation.
KAD2710C-Renesas.pdf
