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Renesas Electronics Components Datasheet

ISL12025 Datasheet

Real-Time Clock/Calendar

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ISL12025
OBSOLETE PRODUCT
NO RECOMMENDED REPLACEMENT
contact our Technical Support Center at
1-888-INTERSIL or www.intersil.com/tsc
Real-Time Clock/Calendar with I2C Bus™ and EEPROM
DATASHEET
FN6371
Rev 4.00
October 12, 2015
The ISL12025 device is a low power real-time clock with
timing and crystal compensation, clock/calender, 64-bit
unique ID, power-fail indicator, two periodic or polled alarms,
intelligent battery backup switching, CPU Supervisor and
integrated 512x8-bit EEPROM, in a 16 Bytes per page
format.
The oscillator uses an external, low-cost 32.768kHz crystal.
The real-time clock tracks time with separate registers for
hours, minutes, and seconds. The device has calendar
registers for date, month, year and day of the week. The
calendar is accurate through 2099, with automatic leap year
correction.
Applications
• Utility Meters
• Audio/Video Components
• Modems
• Network Routers, Hubs, Switches, Bridges
• Cellular Infrastructure Equipment
• Fixed Broadband Wireless Equipment
• Pagers/PDA
• POS Equipment
• Test Meters/Fixtures
• Office Automation (Copiers, Fax)
• Home Appliances
• Computer Products
• Other Industrial/Medical/Automotive
Features
• Real-Time Clock/Calendar
- Tracks Time in Hours, Minutes and Seconds
- Day of the Week, Day, Month and Year
• 64-Bit Unique ID
• Two Non-Volatile Alarms
- Settable on the Second, Minute, Hour, Day of the Week,
Day or Month
- Repeat Mode (Periodic Interrupts)
• Automatic Backup to Battery or Super Cap
• On-Chip Oscillator Compensation
- Internal Feedback Resistor and Compensation
Capacitors
- 64 Position Digitally Controlled Trim Capacitor
- 6 Digital Frequency Adjustment Settings to ±30ppm
• 512x8-Bits of EEPROM
- 16-Bytes Page Write Mode (32 total pages)
- 8 Modes of Block Lock™ Protection
- Single Byte Write Capability
• High Reliability
- Data Retention: 50 years
- Endurance: 2,000,000 Cycles Per Byte
• I2C Interface
- 400kHz Data Transfer Rate
• 800nA Battery Supply Current
• Package Options
- 8 Ld SOIC and 8 Ld TSSOP Packages
• Pb-Free (RoHS Compliant)
Ordering Information
PART
NUMBER
(Note)
TEMP.
PART VRESET RANGE PACKAGE PKG.
MARKING VOLTAGE (°C) (Pb-Free) DWG. #
ISL12025IBZ* 12025 IBZ 2.63V -40 to +85 8 Ld SOIC M8.15
ISL12025IVZ* 2025 IVZ
No longer
available or
supported
2.63V -40 to +85 8 Ld TSSOP M8.173
*Add “-T” suffix for tape and reel. Please refer to TB347 for details on reel
specifications.
NOTE: These Intersil Pb-free plastic packaged products employ special
Pb-free material sets, molding compounds/die attach materials, and
100% matte tin plate plus anneal (e3 termination finish, which is RoHS
compliant and compatible with both SnPb and Pb-free soldering
operations). Intersil Pb-free products are MSL classified at Pb-free peak
reflow temperatures that meet or exceed the Pb-free requirements of
IPC/JEDEC J STD-020.
FN6371 Rev 4.00
October 12, 2015
Page 1 of 28


Renesas Electronics Components Datasheet

ISL12025 Datasheet

Real-Time Clock/Calendar

No Preview Available !

ISL12025
Pinouts
X1
X2
RESET
GND
ISL12025
(8 LD SOIC)
TOP VIEW
18
27
36
45
VDD
VBAT
SCL
SDA
ISL12025
(8 LD TSSOP)
TOP VIEW
VVBDXXANDT12OORLOSUNPG1234PEORRATVEADIL6578ABLE
SCL
SDA
GND
RESET
Pin Descriptions
PIN
NUMBER
SOI TSS
C OP
SY
MB
OL
BRIEF DESCRIPTION
1 3 X1 The X1 pin is the input of an inverting amplifier
and is intended to be connected to one pin of an
external 32.768kHz quartz crystal. X1 can also
be driven directly from a 32.768kHz source.
2 4 X2 The X2 pin is the output of an inverting amplifier
and is intended to be connected to one pin of an
external 32.768kHz quartz crystal.
3 5 RES RESET. This is a reset signal output. This signal
ET notifies a host processor that the “watchdog”
time period has expired or that the voltage has
dropped below a fixed VTRIP threshold. It is an
open drain active LOW output. Recommended
value for the pull-up resistor is 5k. If unused,
connect to ground.
4 6 GN Ground.
D
5 7 SDA Serial Data (SDA) is a bidirectional pin used to
transfer serial data into and out of the device. It
has an open drain output and may be wire
OR’ed with other open drain or open collector
outputs.
6 8 SCL The Serial Clock (SCL) input is used to clock all
serial data into and out of the device. The input
buffer on this pin is always active (not gated).
7 1 VBA This input provides a backup supply voltage to
T the device. VBAT supplies power to the device in
the event that the VDD supply fails. This pin
should be tied to ground if not used.
8 2 VDD Power Supply.
Block Diagram
32.768KHZ
X1
X2
OSC COMPENSATION
OSCILLATOR
FREQUENCY
DIVIDER
1Hz
TIMER
CALENDAR
LOGIC
TIME
KEEPING
REGISTERS
(SRAM)
BATTERY
SWITCH
CIRCUITRY
VDD
VBAT
SCL
SDA
SERIAL
INTERFACE
DECODER
CONTROL
DECODE
LOGIC
CONTROL/
REGISTERS
(EEPROM)
STATUS
REGISTERS
(SRAM)
ALARM
RESET
8
WATCHDOG LOW VOLTAGE
TIMER
RESET
COMPARE
ALARM REGS
(EEPROM)
4k
EEPROM
ARRAY
FN6371 Rev 4.00
October 12, 2015
Page 2 of 28


Part Number ISL12025
Description Real-Time Clock/Calendar
Maker Renesas
PDF Download

ISL12025 Datasheet PDF






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