IDT82V3002A Description
The IDT82V3002A is a WAN PLL with dual reference inputs. It contains a Digital Phase-Locked Loop (DPLL), which generates ST-BUS clocks and framing signals that are phase locked to a 2.048 MHz, 1.544 MHz or 8 kHz input reference. It meets the jitter/wander tolerance, jitter/wander transfer, intrinsic jitter/wander, frequency accuracy, capture range, phase change slope, holdover frequency accuracy and MTIE (Maximum...
IDT82V3002A Key Features
- Supports AT&T TR62411 and Telcordia GR-1244-CORE Stratum 3, Stratum 4 Enhanced and Stratum 4 timing for DS1 interfaces
- Supports ITU-T G.813 Option 1 clocks for 2048 kbit/s interfaces
- Supports ITU-T G.812 Type IV clocks for 1544 kbit/s interface and 2048 kbit/s interfaces
- Supports ETSI ETS 300 011, TBR 4, TBR 12 and TBR 13 timing for E1 interface
- Selectable input reference signal: 8 kHz, 1.544 MHz or 2.048 MHz
- Accepts reference inputs from two independent sources
- Provides eight types of clock signals: C1.5o, C3o, C2o, C4o
- Provides six types of 8 kHz framing pulses: F0o, F8o, F16o
- Holdover frequency accuracy of 0.025 ppm
- Phase slope of 5 ns/125 µs