IDT72285 fifo equivalent, cmos supersync fifo.
* Independent Read and Write Clocks (permit reading and writing
* Choose among the following memory organizations: IDT72275 — 32,768 x 18 IDT72285 — 65,536 x 1.
that need to buffer large amounts of data.
The input port is controlled by a Write Clock (WCLK) input and a Write Enable.
* Master Reset clears entire FIFO
The IDT72275/72285 are exceptionally deep, high speed, CMOS First-In-
* Partial Reset clears data, but retains programmable settings
* Retransmit operation with fixed, low first word data
T R latency .
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