IDT23S09 buffer equivalent, 3.3v zero delay clock buffer.
* Phase-Lock Loop Clock Distribution
* 10MHz to 133MHz operating frequency
* Distributes one clock input to one bank of five and one bank of
four outputs
The zero delay is achieved by aligning the phase between the incoming clock and the output clock, operable within the r.
The IDT23S09 is a high-speed phase-lock loop (PLL) clock buffer, designed to address high-speed clock distribution applications. The zero delay is achieved by aligning the phase between the incoming clock and the output clock, operable within the ra.
Image gallery
TAGS
Download (Size : 189.84KB)