Datasheet4U Logo Datasheet4U.com

ICS98UAE877A - 1.5V LOW-POWER WIDE-RANGE FREQUENCY CLOCK DRIVER

General Description

The PLL clock buffer, ICS98UAE877A, is designed for a VDDQ of 1.5V, an AVDD of 1.5V and differential data input and output levels.

Key Features

  • Low skew, low jitter PLL clock driver.
  • 1 to 10 differential clock distribution.
  • Feedback pins for input to output synchronization.
  • Spread Spectrum tolerant inputs.
  • Auto PD when input signal is at a certain logic state.
  • Available in 52-ball VFBGA and a 40-pin MLF.

📥 Download Datasheet

Datasheet Details

Part number ICS98UAE877A
Manufacturer Renesas
File Size 403.20 KB
Description 1.5V LOW-POWER WIDE-RANGE FREQUENCY CLOCK DRIVER
Datasheet download datasheet ICS98UAE877A Datasheet

📁 Similar Datasheet

Part Number Description Manufacturer
ICS98ULPA877A 1.8V Low-Power Wide-Range Frequency Clock Driver Integrated Device Technology
ICS90C64 Dual Video/Memory Clock Generator Western Digital
ICS90C65 Dual Voltage Video/Memory Clock Generator Integrated Circuit Systems
ICS9111-01 300Mhz Clock Generator Integrated Circuit Systems
ICS9111-03 (ICS9111-03/04) Frequency Generator Integrated Circuit Systems

Other Datasheets by Renesas

Part Number Description
ICS98ULPA877A 1.8V Low-Power Wide-Range Frequency Clock Driver
ICS9112-26 Low Skew Output Buffer
ICS9112A-16 Low Skew Output Buffer
ICS91305 High Performance Communication Buffer
ICS91305I High Performance Communication Buffer

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
DATASHEET 1.5V LOW-POWER WIDE-RANGE FREQUENCY CLOCK DRIVER ICS98UAE877A Description The PLL clock buffer, ICS98UAE877A, is designed for a VDDQ of 1.5V, an AVDD of 1.5V and differential data input and output levels. ICS98UAE877A is a zero delay buffer that distributes a differential clock input pair (CLK_INT, CLK_INC) to ten differential pair of clock outputs (CLKT[0:9], CLKC[0:9]) and one differential pair feedback clock outputs (FB_OUTT, FBOUTC). The clock outputs are controlled by the input clocks (CLK_INT, CLK_INC), the feedback clocks (FB_INT, FB_INC), the LVCMOS program pins (OE, OS) and the Analog Power input (AVDD). When OE is low, the outputs (except FB_OUTT/FB_OUTC) are disabled while the internal PLL continues to maintain its locked-in frequency.