ICS97U877 - 1.8V Wide Range Frequency Clock Driver

Datasheet Summary

Low skew, low jitter PLL clock driver.
1 to 10 differential clock distribution (SSTL_18).
Feedback pins for input to output synchronization.
Spread Spectrum tolerant inputs.
Auto PD when input signal is at a certain logic state Switching Characteristics:.
Period jitter: 40ps.
Half-period jitter: 60ps.
CYCLE - CYCLE jitter 40ps.
OUTPUT - OUTPUT skew: 40ps Pin Configuration 123456 A B C D E F G H J K 1 A CLKT1 B C.

Renesas

Part number	ICS97U877
Manufacturer	Renesas
File Size	827.68 KB
Description	1.8V Wide Range Frequency Clock Driver
Datasheet	ICS97U877 Datasheet
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Published: Feb 19, 2024 |