File Size : 324.47KB ·
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• Higher drive than the 95V857 series devices
• Low skew, low jitter PLL clock driver
• 1 to 10 differential clock distribution (SSTL_2)
• Feedback pins for input to output synchronization
• PD# for power management
• Spread Spectrum-tolerant inputs
• Auto PD when input signal removed
Specification.
