ICS8752 buffer equivalent, lvcmos clock multiplier/zero delay buffer.
* Fully integrated PLL
* Eight LVCMOS outputs, 7Ω typical output impedance
* Selectable LVCMOS CLK0 or CLK1 inputs for redundant clock applications
* Inpu.
The CLK_SEL input determines which reference clock is used. The output divider values of Bank A and B are controlled by.
The ICS8752 is a low voltage, low skew LVCMOS clock generator. With output frequencies up to 240MHz, the ICS8752 is targeted for high performance clock applcations. Along with a fully integrated PLL, the ICS8752 contains frequency configurable output.
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