ICS548A-03 Datasheet | Renesas

LOW SKEW CLOCK INVERTER AND DIVIDER Description The ICS548A-03 is a low cost, low skew, high-performance general purpose clock designed to produce a set of one output clock, one inverted output clock, and one clock divided-by-two. Using our patented Phase-Locked Loop (PLL) techniques, the device operates from a frequency range of 10 MHz to 120 MHz in the PLL mode, and up to 160 MHz in the non-PLL mode. In applications that need to maintain low phase noise in the clock tree, the non-PLL (when S3=S2=1) modes should be used. This chip is not a zero delay buffer. Many applications may be able to use the ICS527 for zero delay dividers. Features - Packaged in 16-pin SOIC...