ICS548A-03 divider equivalent, low skew clock inverter and divider.
* Packaged in 16-pin SOIC (150 mil)
* Input clock up to 160 MHz in the non-PLL mode
* Provides clock outputs of CLK, CLK, and CLK/2
* Low skew (500 ps) on.
that need to maintain low phase noise in the clock tree, the non-PLL (when S3=S2=1) modes should be used.
This chip is n.
The ICS548A-03 is a low cost, low skew, high-performance general purpose clock designed to produce a set of one output clock, one inverted output clock, and one clock divided-by-two. Using our patented Phase-Locked Loop (PLL) techniques, the device o.
Image gallery
TAGS
Download (Size : 292.89KB)