HD74HC541 Datasheet | Renesas

Description The HD74HC540 is an inverting buffer and the HD74HC541 is a non-inverting buffer. The 3-state control gate operates as a two-input NOR such that if either G1 or G2 are high, all eight outputs are in the high-impedance state. Features - High Speed Operation: tpd = 11.5 ns typ (CL = 50 p F) - High Output Current: Fanout of 15 LSTTL Loads - Wide Operating Voltage: VCC = 2 to 6 V - Low Input Current: 1 µA max - Low Quiescent Supply Current: ICC (static) = 4 µA max (Ta = 25°C) - Ordering Information Part Name Package Type Package Code (Previous Code) Package Abbreviation HD74HC540P HD74HC541P DILP-20 pin PRDP0020AC-B P (DP-20NEV) HD74HC540FPEL SOP-20 pin (JEITA) HD74HC541FPEL PRSP0020DD-B (FP-20DAV) HD74HC540RPEL SOP-20 pin (JEDEC) HD74HC541RPEL PRSP0020DC-A (FP-20DBV) HD74HC540TELL TSSOP-20 pin HD74HC541TELL PTSP0020JB-A (TTP-20DAV) Note: Please consult the sales office for the above package availability. Taping Abbreviation (Quantity) - EL (2,000 pcs/reel) EL (1,000 pcs/reel) ELL (2,000 pcs/reel) Function Table Inputs G1 G2 LL LL HX XH H : high level L : low level X : irrelevant Z : off (high-impedance) state of a 3-state output A L H X X Output Y HD74HC540 Rev.2.00 Mar 30, 2006 page 1 of 8 HD74HC540,...