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HD74HC125 - Quad. Bus Buffer Gates

Description

The HD74HC125, HD74HC126 require the 3-state control input C to be taken high to put the output into the high impedance condition, whereas the HD74HC125, HD74HC126 requires the control input to be low to put the output into high impedance.

Features

  • High Speed Operation: tpd = 8 ns typ (CL = 50 pF).
  • High Output Current: Fanout of 15 LSTTL Loads.
  • Wide Operating Voltage: VCC = 2 to 6 V.
  • Low Input Current: 1 µA max.
  • Low Quiescent Supply Current: ICC (static) = 4 µA max (Ta = 25°C).
  • Ordering Information Part Name Package Type Package Code (Previous Code) Package Abbreviation HD74HC125P HD74HC126P DILP-14 pin PRDP0014AB-B (DP-14AV) P HD74HC125FPEL HD74HC126FPEL SOP-14 pin (JEITA).

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Datasheet Details

Part number HD74HC125
Manufacturer Renesas
File Size 116.13 KB
Description Quad. Bus Buffer Gates
Datasheet download datasheet HD74HC125 Datasheet

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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HD74HC125, HD74HC126 Quad. Bus Buffer Gates (with 3-state outputs) REJ03D0565-0300 Rev.3.00 Mar 25, 2009 Description The HD74HC125, HD74HC126 require the 3-state control input C to be taken high to put the output into the high impedance condition, whereas the HD74HC125, HD74HC126 requires the control input to be low to put the output into high impedance.
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