Benefits:
* OE# pins/Suitable for Express Card applications
* PLL or bypass mode/PLL can dejitter incoming clock
* Selectable PLL bandwidth/minimizes jitter p.

Key Specifications:
* Cycle-to-cycle jitter < 50 ps
* Output-to-output skew < 50 ps
* PCIe Gen3 phase jitte.

The 9DB633 zero-delay buffer supports PCIe Gen3 requirements, while being backwards compatible to PCIe Gen2 and Gen1. The 9DB633 is driven by a differential SRC output pair from an IDT 932S421 or 932SQ420 or equivalent main clock generator. It atten.

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