9DB202 Datasheet | Renesas

PCI Express Jitter Attenuator Data Sheet PRODUCT DISCONTINUATION NOTICE - LAST TIME BUY EXPIRES SEPTEMBER 7, 2016 GENERAL DESCRIPTION Features The 9DB202 is a high perfromance 1-to-2 Differential-to-HCSL Jitter Attenuator designed for use in PCI Express™ systems. In some PCI Express™ systems, such as those found in desktop PCs, the PCI Express™ clocks are generated from a low bandwidth, high phase noise PLL frequency synthesizer. In these systems, a jitter-attenuating device may be necessary in order to reduce high frequency random and deterministic jitter ponents from the PLL synthesizer and from the system board. The 9DB202 has two PLL bandwidth modes. In low bandwidth mode, the PLL loop bandwidth is 500k Hz. This setting offers the best jitter attenuation and is still high enough to pass a triangular input spread spectrum profile. In high bandwidth mode, the PLL bandwidth is at 1MHz and allows the PLL to pass more spread spectrum modulation. For serdes which have x10 reference multipliers instead of x12.5 multipliers, each of the two PCI Express™ outputs (PCIEX0:1) can be set for 125MHz instead of 100MHz by configuring the appropriate frequency select pins (FS0:1). - Two 0.7V current mode differential HCSL output pairs - One differential clock input - CLK and n CLK supports the following input types: LVPECL, LVDS, LVHSTL, SSTL, HCSL - Maximum output frequency: 140MHz - Input frequency range: 90MHz - 140MHz - VCO range: 450MHz - 700MHz - Output skew: 110ps (maximum) - Cycle-to-cycle jitter: 110ps (maximum) - RMS phase jitter @ 100MHz, (1.5MHz - 22MHz): 2.42ps (typical) - 3.3V operating supply - 0°C to 70°C ambient operating temperature - Available in lead-free Ro HS pliant package BLOCK DIAGRAM IREF +- Current Set - Industrial temperature information available upon...