8V19N472 synthesizer equivalent, jitter attenuator and clock synthesizer.
▪ High-performance clock RF-PLL ▪ Optimized for low phase noise: <-150dBc/Hz (1MHz offset;
245.76MHz clock) ▪ Dual-PLL architecture
— 1st-PLL stage with external VCXO for.
The device is a member of the high-performance clock family from IDT.
Typical Applications
▪ Low-phase noise clock gene.
Image gallery
Download