8SLVD1212
Description
The 8SLVD1212 is a high-performance differential LVDS fanout buffer. The device is designed for the fanout of high-frequency, very low additive phase-noise clock and data signals.
The 8SLVD1212 is characterized to operate from a 2.5V power supply. Guaranteed output-to-output and part-to-part skew characteristics make the device ideal for clock distribution applications that demand well-defined performance and repeatability. Two selectable differential inputs and twelve low skew outputs are available. The integrated bias voltage reference enables easy interfacing of single-ended signals to the device inputs. The 8SLVD1212 is optimized for low power consumption and low additive phase noise.
Block Diagram
Features
- Twelve low skew, low additive jitter LVDS output pairs
- Two selectable, differential clock input pairs
- Differential PCLK, n PCLK pairs can accept the following differential input levels: LVDS, LVPECL, CML
- Maximum input clock frequency: 2GHz (maximum)
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