8S89296 Datasheet Lvds Programmable Delay Line

Manufacturer: Renesas

Overview: LVDS Programmable Delay Line 8S89296 Datasheet.

Datasheet Details

Part number	8S89296
Manufacturer	Renesas
File Size	544.20 KB
Description	LVDS Programmable Delay Line
Datasheet	8S89296-Renesas.pdf

The 8S89296 is a high performance LVDS programmable delay line.

The delay can vary from 2.2ns to 12.5ns in 10ps steps.

The 8S89296 is characterized to operate from a 2.5V power supply and is guaranteed over industrial temperature range.

One LVDS level output.
One differential clock input pair.
Differential input clock (IN, nIN) can accept the following signaling levels: LVPECL, LVDS, CML.
Maximum frequency: 800MHz.
Programmable Delay Range: 2.2ns to 12.5ns in 10ps steps.
D[10:0] can accept LVPECL, LVCMOS or LVTTL levels.
Full 2.5V supply voltages.
-40°C to 85°C ambient operating temperature.
Available in lead-free (RoHS 6) package IN nIN nEN 0 1 512 GD 0 1 256 GD 0 1 128 GD 0 1.

Part Number	Description
8S89831I	Differential LVPECL-To-LVPECL/ECL Fanout Buffer
8S89832I	1-to-4 Differential-to-LVDS Fanout Buffer
8S89833	1-To-4 Differential-To-LVDS Fanout Buffer w/Internal Termination
8S89834I	2-to-4 LVCMOS/LVTTL-toLVPECL/ECL Clock Multiplexer