Description
The 8S89296 is a high performance LVDS programmable delay line.
Features
- One LVDS level output.
- One differential clock input pair.
- Differential input clock (IN, nIN) can accept the following signaling
levels: LVPECL, LVDS, CML.
- Maximum frequency: 800MHz.
- Programmable Delay Range: 2.2ns to 12.5ns in 10ps steps.
- D[10:0] can accept LVPECL, LVCMOS or LVTTL levels.
- Full 2.5V supply voltages.
- -40°C to 85°C ambient operating temperature.
- Available in lead-free (RoHS 6) package
IN nIN nEN
0
1 512 GD
0
1 256 GD
0
1 128 GD
0
1.
8S89296 Datasheet
