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8S89296 - LVDS Programmable Delay Line

Datasheet Summary

Description

The 8S89296 is a high performance LVDS programmable delay line.

The delay can vary from 2.2ns to 12.5ns in 10ps steps.

The 8S89296 is characterized to operate from a 2.5V power supply and is guaranteed over industrial temperature range.

Features

  • One LVDS level output.
  • One differential clock input pair.
  • Differential input clock (IN, nIN) can accept the following signaling levels: LVPECL, LVDS, CML.
  • Maximum frequency: 800MHz.
  • Programmable Delay Range: 2.2ns to 12.5ns in 10ps steps.
  • D[10:0] can accept LVPECL, LVCMOS or LVTTL levels.
  • Full 2.5V supply voltages.
  • -40°C to 85°C ambient operating temperature.
  • Available in lead-free (RoHS 6) package IN nIN nEN 0 1 512 GD 0 1 256 GD 0 1 128 GD 0 1.

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Datasheet preview – 8S89296

Datasheet Details

Part number 8S89296
Manufacturer Renesas
File Size 544.20 KB
Description LVDS Programmable Delay Line
Datasheet download datasheet 8S89296 Datasheet
Additional preview pages of the 8S89296 datasheet.

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Full PDF Text Transcription

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LVDS Programmable Delay Line 8S89296 Datasheet Description The 8S89296 is a high performance LVDS programmable delay line. The delay can vary from 2.2ns to 12.5ns in 10ps steps. The 8S89296 is characterized to operate from a 2.5V power supply and is guaranteed over industrial temperature range. The delay of the device varies in discrete steps based on a control word. A 10-bit long control word sets the delay in 10ps increments. Also, the input pins IN and nIN default to an equivalent low state when left floating. The control register can accept CMOS or TTL level signals.
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