8S89296 line equivalent, lvds programmable delay line.
▪ One LVDS level output ▪ One differential clock input pair ▪ Differential input clock (IN, nIN) can accept the following signaling
levels: LVPECL, LVDS, CML ▪ Maximum fr.
The 8S89296 is a high performance LVDS programmable delay line. The delay can vary from 2.2ns to 12.5ns in 10ps steps. The 8S89296 is characterized to operate from a 2.5V power supply and is guaranteed over industrial temperature range.
The delay of .
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