* Clock recovery for STM-4 (OC-12/STS-12) and STM-1 (OC-3/STS-3)
* Input: NRZ data (622.08 or 155.52 Mbit/s)
* Output: clock signal (622.08MHz or 155.52MHz) a.

BYPASS set to logic high state is used during factory test. In BYPASS mode (BYPASS and STS12 are at logic high state), .

The 894D115I-04 is a clock and data recovery circuit. The device is designed to extract the clock signal from a NRZ-coded STM-4 (OC-12/STS-12) or STM-1 (OC-3/STS-3) input data signal. The output signals of the device are the recovered clock and retim.

894D115I-01

894-2AC1-F-C

894-2AC1-F-S

894-2AC1-F-V

894-2AC2-F-C

894-2AC2-F-S

894-2AC2-F-V

894-2ACA1-F-C

894-2ACA1-F-S

894-2ACA1-F-V

894-2ACA2-F-C

894-2ACA2-F-S

894-2ACA2-F-V

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