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874S02I - 1:1 Differential-to-LVDS Zero Delay Clock Generator

Description

The 874S02I is a highly versatile 1:1 Differential- to-LVDS Clock Generator and a member of the family of High Performance Clock Solutions from IDT.

Features

  • One differential LVDS output pair and one differential feedback output pair.
  • One differential clock input pair.
  • CLK/nCLK can accept the following differential input levels: LVPECL, LVDS, LVHSTL, SSTL.
  • Input frequency range: 62.5MHz to 1GHz.
  • Output frequency range: 62.5MHz to 1GHz.
  • VCO range: 500MHz.
  • 1GHz.
  • External feedback for "zero delay" clock regeneration with configurable frequencies.
  • Programmable dividers allo.

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Datasheet Details

Part number 874S02I
Manufacturer Renesas
File Size 523.18 KB
Description 1:1 Differential-to-LVDS Zero Delay Clock Generator
Datasheet download datasheet 874S02I Datasheet

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Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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1:1 Differential-to-LVDS Zero Delay Clock Generator 874S02I Datasheet Description The 874S02I is a highly versatile 1:1 Differential- to-LVDS Clock Generator and a member of the family of High Performance Clock Solutions from IDT. The 874S02I has a fully integrated PLL and can be configured as a zero delay buffer, multiplier or divider, and has an output frequency range of 62.5MHz to 1GHz. The reference divider, feedback divider and output divider are each programmable, thereby allowing for the following output-to-input frequency ratios: 8:1, 4:1, 2:1, 1:1, 1:2, 1:4, 1:8. The external feedback allows the device to achieve “zero delay” between the input clock and the output clocks. The PLL_SEL pin can be used to bypass the PLL for system test and debug purposes.
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