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873996 - Differential-to-3.3V LVPECL Zero Delay/Multiplier/Divider

Datasheet Summary

Description

The 873996 is a Zero Delay/Multiplier/Divider with hitless input clock switching capability and a member of the family of low jitter/phase noise devices from IDT.

The 873996 is ideal for use in redundant, fault tolerant clock trees where low phase noise and low jitter are critical.

Features

  • Six differential 3.3V LVPECL outputs.
  • Selectable differential clock inputs.
  • CLKx, nCLKx pair can accept the following differential input levels: LVPECL, LVDS, LVHSTL, HCSL, SSTL.
  • Input clock frequency range: 49MHz to 213.33MHz.
  • Output clock frequency range: 49MHz to 640MHz.
  • VCO range: 490MHz to 640MHz.
  • External feedback for “zero delay” clock regeneration with configurable frequencies.
  • Output skew: 100ps (maximum).

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Datasheet preview – 873996

Datasheet Details

Part number 873996
Manufacturer Renesas
File Size 503.71 KB
Description Differential-to-3.3V LVPECL Zero Delay/Multiplier/Divider
Datasheet download datasheet 873996 Datasheet
Additional preview pages of the 873996 datasheet.

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Full PDF Text Transcription

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Differential-to-3.3V LVPECL Zero Delay/Multiplier/Divider 873996 DATA SHEET GENERAL DESCRIPTION The 873996 is a Zero Delay/Multiplier/Divider with hitless input clock switching capability and a member of the family of low jitter/phase noise devices from IDT. The 873996 is ideal for use in redundant, fault tolerant clock trees where low phase noise and low jitter are critical. The device receives two differential LVPECL clock signals from which it generates 6 LVPECL clock outputs with “zero” delay. The output divider and feedback divider selections also allow for frequency multiplication or division. The 873996 Dynamic Clock Switch (DCS) circuit continuously monitors both input clock signals.
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