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83115 - 1-TO-16 LVCMOS/LVTTL Fanout Buffer

Description

The 83115 is a low skew, 1-to-16 LVCMOS/ LVTTL Fanout Buffer from IDT.

The 83115 single-ended clock input accepts LVCMOS or LVTTL input levels.

The 83115 operates at full 3.3V supply mode over the commercial temperature range.

Features

  • Sixteen LVCMOS / LVTTL outputs, 15 output impedance.
  • One LVCMOS / LVTTL clock input.
  • Maximum output frequency: 200MHz.
  • All inputs are 5V tolerant.
  • Output skew: 250ps (maximum).
  • Part-to-part skew: 800ps (maximum).
  • Additive phase jitter, RMS: 0.09ps (typical).
  • Full 3.3V operating supply.
  • 0°C to 70°C ambient operating temperature.
  • Available in lead-free (RoHS 6) package Block Diagram OE2 VDD 4 IN Q0 Q1 Q.

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Datasheet Details

Part number 83115
Manufacturer Renesas
File Size 321.39 KB
Description 1-TO-16 LVCMOS/LVTTL Fanout Buffer
Datasheet download datasheet 83115 Datasheet

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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Low Skew, 1-TO-16 LVCMOS/LVTTL Fanout Buffer 83115 DATA SHEET General Description The 83115 is a low skew, 1-to-16 LVCMOS/ LVTTL Fanout Buffer from IDT. The 83115 single-ended clock input accepts LVCMOS or LVTTL input levels. The 83115 operates at full 3.3V supply mode over the commercial temperature range. Guaranteed output and part-to-part skew characteristics make the 83115 ideal for those clock distribution applications demanding well defined performance and repeatability. Features • Sixteen LVCMOS / LVTTL outputs, 15 output impedance • One LVCMOS / LVTTL clock input • Maximum output frequency: 200MHz • All inputs are 5V tolerant • Output skew: 250ps (maximum) • Part-to-part skew: 800ps (maximum) • Additive phase jitter, RMS: 0.09ps (typical) • Full 3.
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