8302 Datasheet | Renesas

DESCRIPTION The 8302 is a low skew, 1-to-2 LVCMOS/LVTTL Fanout Buffer. The 8302 hasa single ended clock input. The single endedclock input accepts LVCMOS or LVTTL input levels. The 8302 features a pair of LVCMOS/ LVTTL outputs. The 8302 is characterized at full 3.3V for input VDD,and mixed 3.3V and 2.5V for output operating supply modes (VDDO). Guaranteed output and part-to-part skew characteristics make the 8302 ideal for clock distribution applications demanding well defined performance and repeatibility. FEATURES - 2 LVCMOS / LVTTL outputs - LVCMOS / LVTTL clock input accepts LVCMOS or LVTTL input levels - Maximum output frequency: 200MHz - Output skew: 25ps (typical) - Part-to-part skew: 250ps (typical) - Small 8 lead SOIC package saves board space - Full 3.3V or 3.3V core, 2.5V supply modes - 0°C to 70°C ambient operating temperature - Lead-Free package fully Ro HS pliant BLOCK DIAGRAM Q0 Q1 ©2016 Integrated Device Technology, Inc PIN ASSIGNMENT VDDO VDD CLK 1 2 3 4 8 Q0 7 GND 6 VDDO 5 Q1 8-Lead SOIC 3.8mm x 4.8mm, x 1.47mm package body M Package Top View 1 Revision D March 4, 2016 8302 Data Sheet TABLE 1. PIN DESCRIPTIONS Number Name Type Description 1, 6 VDDO Power Output supply pins. 2 VDD Power Core supply pin. 3 CLK Input Pulldown LVCMOS / LVTTL clock...