* Composite clock inputs (IN1 and IN2) accept 64 kHz synchronization interface signals per ITU-T G.703
* Differential reference inputs (IN3 to IN8) accept clock f.

* APLL3 is Voltage Controlled Crystal Oscillator (VCXO) based and generates clocks with jitter <0.3 ps RMS (10 kHz t.

82P33714

82P33724

82P33741

82P33810

82P33813

82P33814

82P33831

82P33910

82P33910-1

82P33913

82P33913-1

82P33914

82P33914-1

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