70V24L Datasheet | Renesas

Features - True Dual-Ported memory cells which allow simultaneous reads of the same memory location - High-speed access IDT70V35 - mercial: 15ns (max.) - Industrial: 20ns IDT70V34 - mercial: 15ns (max.) IDT70V25 - mercial: 15/35ns (max.) - Industrial: 20/25ns IDT70V24 - mercial: 15//35/55ns (max.) - Industrial: 15/20ns - Low-power operation - IDT70V35/34L Active: 415m W (typ.) Standby: 660μW (typ.) Functional Block Diagram R/WL UBL - IDT70V25/24S - IDT70V25/24L Active: 400m W (typ.) Active: 380m W (typ.) Standby: 3.3m W (typ.) Standby: 660μW (typ.) - Separate upper-byte and lower-byte control for multiplexed bus patibility - IDT70V35/34 (IDT70V25/24) easily expands data bus width to 36 bits (32 bits) or more using the Master/Slave select when cascading more than one device - M/S = VIH for BUSY output flag on Master M/S = VIL for BUSY input on Slave - BUSY and Interrupt Flag - On-chip port arbitration logic - Full on-chip hardware support of semaphore signaling between ports - Fully asynchronous operation from either port - LVTTL-patible, single 3.3V (±0.3V) power supply - Available in a 100-pin TQFP (IDT70V35/34) & (IDT70V25/24), and 84-pin PLCC (IDT70V24) - Industrial temperature range (-40°C to +85°C) is available for selected speeds - Green parts available, see ordering information R/WR UBR LBL CEL OEL I/O9L-I/O17L(5) I/O0L-I/O8L(4) BUSYL(2,3) I/O Control I/O Control A12L(1) A0L Address...