70V24L
Overview
- True Dual-Ported memory cells which allow simultaneous reads of the same memory location
- High-speed access IDT70V35 - Commercial: 15ns (max.) - Industrial: 20ns IDT70V34 - Commercial: 15ns (max.) IDT70V25 - Commercial: 15/35ns (max.) - Industrial: 20/25ns IDT70V24 - Commercial: 15//35/55ns (max.) - Industrial: 15/20ns
- Low-power operation - IDT70V35/34L Active: 415mW (typ.) Standby: 660μW (typ.) Functional Block Diagram R/WL UBL - IDT70V25/24S - IDT70V25/24L Active: 400mW (typ.) Active: 380mW (typ.) Standby: 3.3mW (typ.) Standby: 660μW (typ.)
- Separate upper-byte and lower-byte control for multiplexed bus compatibility
- IDT70V35/34 (IDT70V25/24) easily expands data bus width to 36 bits (32 bits) or more using the Master/Slave select when cascading more than one device
- M/S = VIH for BUSY output flag on Master M/S = VIL for BUSY input on Slave
- BUSY and Interrupt Flag
- On-chip port arbitration logic
- Full on-chip hardware support of semaphore signaling between ports
- Fully asynchronous operation from either port
