V7001 controller equivalent, sdr-sdram memory controller.
* JEDEC standard SDR-SDRAM supported
* Transaction pipeline for maximum utilization of the Memory Bus
* 3 Request buffers for transaction pipeline
* Suppo.
* Can be easily interfaced to any SoC designs that need to interact with SDR-SDRAM
* In embedded memory intensiv.
Document
* Self checking Verification Suite
* Synthesis Scripts
* Scripts for STA & DFT (optional)
QCL_10208_DF_02_Datasheet_rev101
QualCore Logic, Inc.
1289, ANVILWOOD AVENUE SUNNYVALE, CA - 94089, USA Tel: 408 541 0730 Fax: 408 541 07.
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