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HYS72T64020HP - 240-Pin Registered DDR2 SDRAM Modules

This page provides the datasheet information for the HYS72T64020HP, a member of the HYS72T32000HP 240-Pin Registered DDR2 SDRAM Modules family.

Datasheet Summary

Description

devices and a PLL for the clock distribution.

This reduces capacitive loading to the system bus, but adds one cycle to the SDRAM timing.

Decoupling capacitors are mounted on the PCB board.

Features

  • Programmable CAS Latencies (3, 4 and 5), Burst Length (4 & 8) and Burst Type.
  • Auto Refresh (CBR) and Self Refresh.
  • Average Refresh Period 7.8 µs at a T lower than 85 °C, 3.9 µs between 85 °C and 95 °C.
  • Programmable self refresh rate via EMRS2 setting.
  • All inputs and outputs SSTL_18 compatible.
  • Off-Chip Driver Impedance Adjustment (OCD) and On-Die Termination (ODT).
  • Serial Presence Detect with E2PROM.
  • Based on standard refer.

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Datasheet Details

Part number HYS72T64020HP
Manufacturer Qimonda AG
File Size 1.04 MB
Description 240-Pin Registered DDR2 SDRAM Modules
Datasheet download datasheet HYS72T64020HP Datasheet
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September 2006 www.DataSheet4U.com HYS72T32000HP–[3S/3.7]–A HYS72T64001HP–[3S/3.7]–A HYS72T64020HP–[3S/3.7]–A 240-Pin Registered DDR2 SDRAM Modules DDR2 SDRAM RDIMM SDRAM RoHs Compilant Internet Data Sheet Rev. 1.01 Internet Data Sheet www.DataSheet4U.com HYS72T[32/64]xxxHP–[3S/3.7]–A Registered DDR2 SDRAM Modules HYS72T32000HP–[3S/3.7]–A, HYS72T64001HP–[3S/3.7]–A, HYS72T64020HP–[3S/3.7]–A Revision History: 2006-09, Rev. 1.01 Page All All 24 Subjects (major changes since last revision) Qimonda update Adapted internet edition Modified AC Timing Parameters Previous Revision: 2006-03, Rev. 1.0 We Listen to Your Comments Any information within this document that you feel is wrong, unclear or missing at all? Your feedback will help us to continuously improve the quality of this document.
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