* Detects errors on the channel and reports them to the host memory controller.
* Automatic DDR2 DRAM Bus Calibration.
* Automatic Channel Calibration.
* .

* Module organisation one rank 64M × 72, one rank 128M × 72, two ranks 128M × 72, two ranks 256M ×72
* JEDEC St.

using an Industry Standard High-Speed Differential Point-toPoint Link Interface at 1.5 V. The Advanced Memory Buffer also allows buffering of memory traffic to support large memory capacities. All memory control for the DRAM resides in the host, incl.

HYS72T256020GR

HYS72T256020GR-37-A

HYS72T256020GR-5-A

HYS72T256020HFA-3.7-A

HYS72T256020HFA-3S-A

HYS72T256020HFN-3.7-A

HYS72T256020HFN-3S-A

HYS72T256020HR

HYS72T256020HR-37-A

HYS72T256020HR-5-A

HYS72T256023HR-5-A

HYS72T25620HFD-3S-B

HYS72T256220GR

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