HYS72T256520HFD-3S-B Datasheet | Qimonda AG

Overview Features - Detects errors on the channel and reports them to the host memory controller. - Automatic DDR2 DRAM Bus Calibration. - Automatic Channel Calibration. - Full Host Control of the DDR2 DRAMs. - Over-Temperature Detection and Alert. - Hot Add-on and Hot Remove Capability. - MBIST and IBIST Test Functions. - Transparent Mode for DRAM Test Support. - Low profile: 133.35mm x 30.35 mm - 240 Pin gold plated card connector with 1.00 mm contact centers (JEDEC standard pending). - Based on JEDEC standard reference card designs (Jedec standard pending). - SPD (Serial Presence Detect) with 256 Byte serial E2PROM.Performance: - Ro HS pliant Products1) This chapter describes the main characteristics of the 240-Pin Fully-Buffered DDR2 SDRAM Modules product family. - 240-pin Fully-Buffered ECC Dual-In-Line DDR2 SDRAM Module for PC, Workstation and Server main memory applications. - Module organisation one rank 64M × 72, one rank 128M × 72, two ranks 128M × 72, two ranks 256M ×72 - JEDEC Standard Double Data Rate 2 Synchronous DRAMs (DDR2 SDRAMs) with 1.8 V (± 0.1 V) power supply. - Built with 512Mb DDR2 SDRAMs in 60-ball FBGA Chipsize Packages. - Re-drive and re-sync of all address, mand, clock and data signals using AMB (Advanced Memory Buffer). - High-Speed Differential Point-to-Point Link Interface at 1.5 V (Jedec standard pending). - Host Interface and AMB ponent industry standard pliant. - Supports SMBus protocol interface for access to the AMB configuration registers. TABLE 1 Performance for DDR2- 667 Product Type Speed Code Speed Grade max. Clock Frequency @CL5 @CL4 @CL3 min. RAS-CAS-Delay min. Row Precharge Time min. Row Active Time min. Row Cycle Time - 3S PC2- 5300 5- 5- 5 Unit - MHz MHz MHz ns ns ns ns f CK5 f CK4 f CK3 t RCD t RP t RAS t RC 333 266 200 15 15 45 60 1) Ro HS pliant Product: Restriction of the use of certain hazardous substances (Ro HS) in electrical and electronic equipment as defined...