Description
The memory array is designed with 256-Mbit Double-DataRate-Two (DDR2) Synchronous DRAMs.
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A module family are unbuffered DIMM modules “UDIMMs”
Features
- for average self refresh and self refresh rate to Feature list Chapter 3 Chapter 3 Chapter 4 Chapter 4 Chapter 5 Updated IDD Currents Corrected note 4 - Table 18 Updated SPD Codes SPD Codes update: Byte 49 Bit 0 = 1 (HighT_SRFEntry) for all product types Package Outlines updated
Previous Revision: 2006-04, Rev. 1.4
Previous Revision: 2005-09, Rev. 1.3
Previous Revision: 2005-05, Rev. 1.2
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