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HYB18T256161BF-28 - 256-Mbit x16 DDR2 SDRAM

Download the HYB18T256161BF-28 datasheet PDF. This datasheet also covers the HYB18T256161BF-20 variant, as both devices belong to the same 256-mbit x16 ddr2 sdram family and are provided as variant models within a single manufacturer datasheet.

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Note: The manufacturer provides a single datasheet file (HYB18T256161BF-20_QimondaAG.pdf) that lists specifications for multiple related part numbers.

Datasheet Details

Part number HYB18T256161BF-28
Manufacturer Qimonda AG
File Size 1.38 MB
Description 256-Mbit x16 DDR2 SDRAM
Datasheet download datasheet HYB18T256161BF-28 Datasheet

Overview

June 2007 www.DataSheet4U.com HYB18T256161BF–20/25/28 256-Mbit x16 DDR2 SDRAM DDR2 SDRAM RoHS compliant Internet Data Sheet Rev.

1.20 Internet Data Sheet www.DataSheet4U.com HYB18T256161BF–20/25/28 256-Mbit Double-Data-Rate-Two SDRAM HYB18T256161BF–20/25/28 Revision History: 2007-06, Rev.

1.20 Page All All 94-101 82-86 All Subjects (major changes since last revision) Typos corrected Final Data Sheet added chapter 7 explaining AC timing measurement condition (reference load ; slew rate ; set up & hold timing references ; derating values for input /command ,data ) setup & hold timings are changed with reference to Industrial standard definition removed all the occurances of RDQS as it in not used in graphics (x16) Previous Revision: Rev.

Key Features

  • The 256-Mbit Double-Data-Rate-Two SDRAM offers the following key features:.
  • Data masks (DM) for write data.
  • 1.8 V ± 0.1V VDD for [.
  • 20/.
  • 25/.
  • 28].
  • 1.8 V ± 0.1V VDDQ for [.
  • 20/.
  • 25/.
  • 28].
  • Posted CAS by programmable additive latency for better.
  • DRAM organizations with 16 data in/outputs command and data bus efficiency.
  • Double Data Rate architecture:.
  • Off-Chip-Driver impedance adjustment (OCD).

More Datasheets from Qimonda AG

Part Number Description
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