HYS72T256023HR-5-A modules equivalent, 240-pin registered ddr2 sdram modules.
* Auto Refresh (CBR) and Self Refresh
* Average Refresh Period 7.8 µs at a TCASE lower than 85 °C, 3.9µs between 85 °C and 95 °C.
* All inputs and outputs SST.
* Two rank 256M × 72, 512M × 72 module organization and 2 × 128M × 8, 2 × 256M × 4 chip organization
* 2GByte, 4.
capacitive loading to the system bus, but adds one cycle to the SDRAM timing. Decoupling capacitors are mounted on the PCB board. The DIMMs feature serial presence detect based on a serial E2PROM device using the 2-pin I2C protocol. The first 128 byt.
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