HYI39SC128160FE dram equivalent, 128-mbit synchronous dram.
*
*
*
*
*
*
*
*
* Data Mask for Read / Write control (×8) Data Mask for Byte Control (×16) Auto Refresh (CBR) and Self Refresh Power D.
output circuits are synchronized with the positive edge of an externally supplied clock. Operating the four memory banks in an interleave fashion allows random access operation to occur at a higher rate than is possible with standard DRAMs. A sequent.
Image gallery
TAGS
Manufacturer
Related datasheet
Download (Size : 1.15MB)