HYB39S128800FE, HYB39S128160FE - 128-MBit Synchronous DRAM

Qimonda

Datasheet Details

Part number	HYB39S128800FE, HYB39S128160FE
Manufacturer	Qimonda
File Size	1.39 MB
Description	128-MBit Synchronous DRAM
Datasheet	HYB39S128160FE_Qimonda.pdf
Note	This datasheet PDF includes multiple part numbers: HYB39S128800FE, HYB39S128160FE. Please refer to the document for exact specifications by model.

The HY[B/I]39S128[40/80/16][0/7]F[E/T](L) are four bank Synchronous DRAM’s organized as 32 MBit x4, 16 MBit x8 and 8 Mbit x16 respectively.

Data Mask for Read / Write control (x4, x8) Data Mask for Byte Control (x16) Auto Refresh (CBR) and Self Refresh Power Down and Clock Suspend Mode 4096 refresh cycles / 64 ms (15.6 μs) Random Column Address every CLK (1-N Rule) Single 3.3 V ± 0.3 V Power Supply LVTTL Interface Plastic Packages: P(G).
TSOPII.
54 400 mil width This chapter lists all main features of the product family HY[B/I]39.

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Published: Apr 10, 2010 |