HYB25DC512800BF, HYB25DC512160B - 512-Mbit Double-Data-Rate SDRAM

Qimonda

Datasheet Details

Part number	HYB25DC512800BF, HYB25DC512160B
Manufacturer	Qimonda
File Size	1.97 MB
Description	512-Mbit Double-Data-Rate SDRAM
Datasheet	HYB25DC512160B_Qimonda.pdf
Note	This datasheet PDF includes multiple part numbers: HYB25DC512800BF, HYB25DC512160B. Please refer to the document for exact specifications by model.

The 512-Mbit Double-Data-Rate SDRAM is a high-speed CMOS, dynamic random-access memory containing 536,870,912 bits.

This chapter lists all main features of the product family HYB25DC512[80/16]0B[E/F] and the ordering information. Double data rate architecture: two data transfers per clock cycle Bidirectional data strobe (DQS) is transmitted and received with data, to be used in capturing data at the receiver DQS is edge-aligned with data for reads and is center-aligned with data for writes Differential clock inputs (CK and CK) Four internal banks for concurrent operation Data mask (DM) for write data DLL al.

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Published: Apr 12, 2009 |