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HYB25D512400CF - (HYB25D512xx0Cx) DDR SDRAM

This page provides the datasheet information for the HYB25D512400CF, a member of the HYB25D512400CE (HYB25D512xx0Cx) DDR SDRAM family.

Description

Read and write accesses to the DDR SDRAM are burst oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence.

Accesses begin with the registration of an Active command, which is then followed by a Read or Write command.

Features

  • Burst Lengths: 2, 4, or 8 CAS Latency: 2, 2.5, 3 Auto Precharge option for each burst access Auto Refresh and Self Refresh Modes RAS-lockout supported tRAP=tRCD 7.8 µs Maximum Average Periodic Refresh Interval 2.5 V (SSTL_2 compatible) I/O VDDQ = 2.5 V ± 0.2 V VDD = 2.5 V ± 0.2 V P-TFBGA-60-11 package P-TSOPII-66-1 package RoHS Compliant Products1).
  • Double data rate a.

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Datasheet preview – HYB25D512400CF

Datasheet Details

Part number HYB25D512400CF
Manufacturer Qimonda
File Size 1.90 MB
Description (HYB25D512xx0Cx) DDR SDRAM
Datasheet download datasheet HYB25D512400CF Datasheet
Additional preview pages of the HYB25D512400CF datasheet.

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Full PDF Text Transcription

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September 2006 HYB25D512400C[E/T/F/C](L) HYB25D512800C[E/T/F/C](L) HYB25D512160C[E/T/F](L) www.DataSheet4U.com DDR SDRAM RoHS Compliant Products Internet Data Sheet Rev. 1.31 Internet Data Sheet HYB25D512[400/160/800]C[E/T/F/C](L) 512-Mbit Double-Data-Rate SDRAM HYB25D512400C[E/T/F/C](L), HYB25D512800C[E/T/F/C](L), HYB25D512160C[E/T/F](L) Revision History: 2006-09, Rev. 1.31 Page www.DataSheet4U.com Subjects (major changes since last revision) Qimonda update Adapted internet edition All All Previous Revision: 2006-05, Rev. 1.3 10 10 Added the components HYB25D512160CT-6, HYB25D512160CT-5, HYB25D512800CFL-6 HYB25D512800CFL-5, HYB25D512160CFL-6 Correct the name HYB25D512400CFL-6 Previous Revision: 2006-03, Rev. 1.
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