HYB18TC1G160AF
Key Features
- The 1-Gbit Double-data-Rate SDRAM offers the following key features
- Off-Chip-Driver impedance adjustment (OCD) and On
- DRAM organizations with 8, 16 data in/outputs
- Auto-Precharge operation for read and write bursts
- Double Data Rate architecture: two data transfers per
- Auto-Refresh, Self-Refresh and power saving PowerDown modes clock cycle four internal banks for concurrent operation
- Average Refresh Period 7.8 µs at a TCASE lower than
- Programmable self refresh rate via EMRS2 setting
- Differential clock inputs (CK and CK)
- DCC enabling via EMRS2 setting
