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P4C167L - ULTRA HIGH SPEED 16K X 1 STATIC CMOS RAMS

Download the P4C167L datasheet PDF (P4C167 included). The manufacturer datasheet provides complete specifications, pinout details, electrical characteristics, and typical applications for ultra high speed 16k x 1 static cmos rams.

Description

The P4C167/L are 16,384-bit high speed static RAMs organized as 16K x 1.

The CMOS memories require no clocks or refreshing and have equal access and cycle times.

The RAMs operate from a single 5V ± 10% tolerance power supply.

Features

  • Full CMOS, 6T Cell High Speed (Equal Access and Cycle Times).
  • 10/12/15/20/25 ns (Commercial).
  • 12/15/20/25/35 ns (Industrial).
  • 15/20/25/35/45 ns (Military) www. DataSheet4U. com Separate Data I/O Three-State Output TTL Compatible Output Fully TTL Compatible Inputs Standard Pinout (JEDEC Approved).
  • 20-Pin 300 mil DIP.
  • 20-Pin 300 mil SOJ.
  • 20-Pin LCC Low Power Operation Single 5V±10% Power Supply Data Retention with 2.0V Supply (P4C167L Military).

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (P4C167_PyramidSemiconductorCorporation.pdf) that lists specifications for multiple related part numbers.

Datasheet Details

Part number P4C167L
Manufacturer Pyramid Semiconductor Corporation
File Size 228.99 KB
Description ULTRA HIGH SPEED 16K X 1 STATIC CMOS RAMS
Datasheet download datasheet P4C167L Datasheet
Other Datasheets by Pyramid Semiconductor Corporation

Full PDF Text Transcription

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P4C167/P4C167L ULTRA HIGH SPEED 16K X 1 STATIC CMOS RAMS FEATURES Full CMOS, 6T Cell High Speed (Equal Access and Cycle Times) – 10/12/15/20/25 ns (Commercial) – 12/15/20/25/35 ns (Industrial) – 15/20/25/35/45 ns (Military) www.DataSheet4U.com Separate Data I/O Three-State Output TTL Compatible Output Fully TTL Compatible Inputs Standard Pinout (JEDEC Approved) – 20-Pin 300 mil DIP – 20-Pin 300 mil SOJ – 20-Pin LCC Low Power Operation Single 5V±10% Power Supply Data Retention with 2.0V Supply (P4C167L Military) DESCRIPTION The P4C167/L are 16,384-bit high speed static RAMs organized as 16K x 1. The CMOS memories require no clocks or refreshing and have equal access and cycle times. The RAMs operate from a single 5V ± 10% tolerance power supply.
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