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Power Semiconductors
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AT1007S24 Datasheet Preview

AT1007S24 Datasheet

PHASE CONTROL THYRISTOR

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AT1007S24 pdf
ANSALDO
Ansaldo Trasporti s.p.a.
Unita' Semiconduttori
Via N. Lorenzi 8 - I 16152 GENOVA - ITALY
Tel. int. +39/(0)10 6556549 - (0)10 6556488
Fax Int. +39/(0)10 6442510
Tx 270318 ANSUSE I -
PHASE CONTROL THYRISTOR
FINAL SPECIFICATION
feb 97 - ISSUE : 06
AT1007
Repetitive voltage up to
Mean on-state current
Surge current
2400 V
1270 A
19 kA
Symbol Characteristic
BLOCKING
Conditions
Tj
[°C] Value Unit
V RRM
Repetitive peak reverse voltage
125 2400
V
V RSM
Non-repetitive peak reverse voltage
125 2500
V
V DRM
Repetitive peak off-state voltage
125 2400
V
I RRM
Repetitive peak reverse current
V=VRRM
125 50
mA
I DRM
Repetitive peak off-state current
V=VDRM
125 50
mA
CONDUCTING
I T (AV)
Mean on-state current
180° sin, 50 Hz, Th=55°C, double side cooled
1270
A
I T (AV)
Mean on-state current
180° sin, 50 Hz, Tc=85°C, double side cooled
1035
A
I TSM
Surge on-state current
sine wave, 10 ms
125 19
kA
I² t I² t
without reverse voltage
1805 x1E3 A²s
V T On-state voltage
On-state current = 2900 A
25 2
V
V T(TO)
Threshold voltage
125 1.15
V
r T On-state slope resistance
125 0.308
mohm
SWITCHING
di/dt Critical rate of rise of on-state current, min. From 75% VDRM up to 1350 A, gate 10V 5ohm 125 200 A/µs
dv/dt
Critical rate of rise of off-state voltage, min. Linear ramp up to 70% of VDRM
125 500
V/µs
td
Gate controlled delay time, typical
VD=100V, gate source 25V, 10 ohm , tr=.5 µs 25 1.3
µs
tq
Circuit commutated turn-off time, typical
dV/dt = 20 V/µs linear up to 75% VDRM
320 µs
Q rr Reverse recovery charge
di/dt=-20 A/µs, I= 880 A
125 µC
I rr Peak reverse recovery current
VR= 50 V
A
I H Holding current, typical
VD=5V, gate open circuit
25 300
mA
I L Latching current, typical
VD=5V, tp=30µs
25 700
mA
GATE
V GT
Gate trigger voltage
VD=5V
25 3.5
V
I GT Gate trigger current
VD=5V
25 300
mA
V GD
Non-trigger gate voltage, min.
VD=VDRM
125 0.25
V
V FGM
Peak gate voltage (forward)
30 V
I FGM
Peak gate current
10 A
V RGM
Peak gate voltage (reverse)
5V
P GM
Peak gate power dissipation
Pulse width 100 µs
150 W
P G Average gate power dissipation
2W
MOUNTING
R th(j-h)
Thermal impedance, DC
Junction to heatsink, double side cooled
26 °C/kW
R th(c-h)
Thermal impedance
Case to heatsink, double side cooled
6 °C/kW
T j Operating junction temperature
F Mounting force
Mass
-30 / 125
18.0 / 20.0
500
°C
kN
g
ORDERING INFORMATION : AT1007 S 24
standard specification
VDRM&VRRM/100



Power Semiconductors
Power Semiconductors

AT1007S24 Datasheet Preview

AT1007S24 Datasheet

PHASE CONTROL THYRISTOR

No Preview Available !

AT1007S24 pdf
AT1007 PHASE CONTROL THYRISTOR
FINAL SPECIFICATION feb 97 - ISSUE : 06
ANSALDO
Th [°C]
130
120
110
100
90
80
70
60
50
0
PF(AV) [W]
3000
2500
2000
1500
1000
500
0
0
DISSIPATION CHARACTERISTICS
SQUARE WAVE
30°
60°
90°
120°
180°
500 1000
IF(AV) [A]
DC
1500
2000
120°
90°
180°
60°
30°
DC
500
1000
1500
IF(AV) [A]
2000


Part Number AT1007S24
Description PHASE CONTROL THYRISTOR
Maker Power Semiconductors
Total Page 4 Pages
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