PO74HSTL314A buffer equivalent, 3.3v 2:4 differential clock/data fanout buffer.
. Patented Technology . Four HSTL differential outputs . The two pair of LVDS/LVPECL/HSTL/ differential or single-ended inputs . Hot-swappable/-insertable . Operating fr.
The device is implemented on 0.35um CMOS technology and has a fully differential internal architecture that is optimize.
The PO74HSTL314 is a low-skew, 2-to-4 differential fanout buffer targeted to meet the requirements of high-performance clock and data distribution applications. The device is implemented on 0.35um CMOS technology and has a fully differential interna.
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