PSMN015-100P Datasheet | Philips Semiconductors

FEATURES - ’Trench’ technology - Very low on-state resistance - Fast switching - Low thermal resistance g PSMN015-100B, PSMN015-100P QUICK REFERENCE DATA d SYMBOL VDSS = 100 V ID = 75 A RDS(ON) ≤ 15 mΩ s GENERAL DESCRIPTION Silicon MAX products use the latest Philips Trench technology to achieve the lowest possible on-state resistance in each package at each voltage rating. Applications:- d.c. to d.c. converters - switched mode power supplies The PSMN015-100P is supplied in the SOT78 (TO220AB) conventional leaded package. The PSMN015-100B is supplied in the SOT404 surface mounting package. PINNING PIN 1 2 3 tab gate drain1 source drain DESCRIPTION SOT78 (TO220AB) tab SOT404 (D2PAK) tab 1 23 LIMITING VALUES Limiting values in accordance with the Absolute Maximum System (IEC 134) SYMBOL PARAMETER VDSS VDGR VGS ID IDM PD Tj, Tstg Drain-source voltage Drain-gate voltage Gate-source voltage Continuous drain current Pulsed drain current Total power dissipation Operating junction and storage temperature CONDITIONS Tj = 25 ˚C to 175˚C Tj = 25 ˚C to 175˚C; RGS = 20 kΩ Tmb = 25 ˚C Tmb = 100 ˚C Tmb = 25 ˚C Tmb = 25 ˚C MIN. - 55 MAX. 100 100 ± 20 752 53 240 230 175 UNIT V V V A A A W ˚C 1 It is not possible to make connection to pin:2 of the SOT404 package 2 Maximum continuous current limited by package August 1999 1 Rev 1.100 Philips Semiconductors Product specification N-channel Trench MOS™ transistor AVALANCHE ENERGY LIMITING VALUES PSMN015-100B, PSMN015-100P Limiting values in accordance with the Absolute Maximum System (IEC 134) SYMBOL PARAMETER EAS Non-repetitive avalanche energy Non-repetitive avalanche current CONDITIONS Unclamped inductive load, IAS = 74 A; tp = 100 µs; Tj prior to avalanche = 25˚C; VDD ≤ 50 V; RGS = 50 Ω; VGS = 10 V; refer to fig:15 MIN. MAX. 481 UNIT m J - 75 THERMAL RESISTANCES SYMBOL PARAMETER Rth j-mb Rth j-a Thermal resistance junction to mounting base Thermal resistance junction to ambient CONDITIONS TYP. SOT78...