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Philips

PSMN010-55D Datasheet Preview

PSMN010-55D Datasheet

N-channel logic level TrenchMOS transistor

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Philips Semiconductors
Product specification
N-channel logic level TrenchMOStransistor
PSMN010-55D
FEATURES
’Trench’ technology
• Very low on-state resistance
• Fast switching
• Logic level compatible
SYMBOL
d
g
s
QUICK REFERENCE DATA
VDSS = 55 V
ID = 75 A
RDS(ON) 10.5 m(VGS = 10 V)
RDS(ON) 12 m(VGS = 5 V)
GENERAL DESCRIPTION
SiliconMAX products use the latest
Philips Trench technology to
achieve the lowest possible
on-state resistance in each
package at each voltage rating.
Applications:-
• d.c. to d.c. converters
• switched mode power supplies
The PSMN010-55D is supplied in
the SOT428 (Dpak) surface
mounting package.
PINNING
PIN
DESCRIPTION
1 gate
2 drain1
3 source
tab drain
SOT428 (DPAK)
tab
2
13
LIMITING VALUES
Limiting values in accordance with the Absolute Maximum System (IEC 134)
SYMBOL PARAMETER
CONDITIONS
VDSS
VDGR
VGS
VGSM
ID
IDM
PD
Tj, Tstg
Drain-source voltage
Drain-gate voltage
Continuous gate-source
voltage
Peak pulsed gate-source
voltage
Continuous drain current
Pulsed drain current
Total power dissipation
Operating junction and
storage temperature
Tj = 25 ˚C to 175˚C
Tj = 25 ˚C to 175˚C; RGS = 20 k
Tj 150 ˚C
Tmb = 25 ˚C; VGS = 5 V
Tmb = 100 ˚C; VGS = 5 V
Tmb = 25 ˚C
Tmb = 25 ˚C
MIN.
-
-
-
-
-
-
-
-
- 55
MAX.
55
55
± 15
± 20
752
57
240
125
175
UNIT
V
V
V
V
A
A
A
W
˚C
1 It is not possible to make connection to pin 2 of the SOT428 package.
2 Continuous current rating limited by package.
October 1999
1
Rev 1.200




Philips

PSMN010-55D Datasheet Preview

PSMN010-55D Datasheet

N-channel logic level TrenchMOS transistor

No Preview Available !

Philips Semiconductors
Product specification
N-channel logic level TrenchMOStransistor
PSMN010-55D
AVALANCHE ENERGY LIMITING VALUES
Limiting values in accordance with the Absolute Maximum System (IEC 134)
SYMBOL PARAMETER
CONDITIONS
EAS
Non-repetitive avalanche
Unclamped inductive load, IAS = 74 A;
energy
tp = 100 µs; Tj prior to avalanche = 25˚C;
VDD 25 V; RGS = 50 ; VGS = 5 V
IAS Non-repetitive avalanche
current
MIN.
-
MAX.
264
UNIT
mJ
- 75 A
THERMAL RESISTANCES
SYMBOL PARAMETER
Rth j-mb
Rth j-a
Thermal resistance junction
to mounting base
Thermal resistance junction
to ambient
CONDITIONS
MIN. TYP. MAX. UNIT
- - 1.2 K/W
SOT428 package, pcb mounted, minimum - 50 - K/W
footprint
ELECTRICAL CHARACTERISTICS
Tj= 25˚C unless otherwise specified
SYMBOL PARAMETER
CONDITIONS
V(BR)DSS
VGS(TO)
RDS(ON)
IGSS
IDSS
Qg(tot)
Qgs
Qgd
td on
tr
td off
tf
Ld
Ls
Drain-source breakdown
voltage
Gate threshold voltage
Drain-source on-state
resistance
Gate source leakage current
Zero gate voltage drain
current
Total gate charge
Gate-source charge
Gate-drain (Miller) charge
VGS = 0 V; ID = 0.25 mA;
Tj = -55˚C
VDS = VGS; ID = 1 mA
Tj = 175˚C
Tj = -55˚C
VGS = 10 V; ID = 25 A
VGS = 5 V; ID = 25 A
VGS = 4.5 V; ID = 25 A
VGS = 5 V; ID = 25 A; Tj = 175˚C
VGS = ±10 V; VDS = 0 V
VDS = 25 V; VGS = 0 V;
Tj = 175˚C
ID = 75 A; VDD = 44 V; VGS = 5 V
Turn-on delay time
Turn-on rise time
Turn-off delay time
Turn-off fall time
VDD = 30 V; RD = 1.2 ;
VGS = 10 V; RG = 10
Resistive load
Internal drain inductance
Internal source inductance
Measured tab to centre of die
Measured from source lead to source
bond pad
Ciss Input capacitance
Coss Output capacitance
Crss Feedback capacitance
VGS = 0 V; VDS = 20 V; f = 1 MHz
MIN. TYP. MAX. UNIT
55 -
-V
42 -
-V
1 1.5 2
V
0.5 -
-V
- - 2.3 V
- 7.4 10.5 m
- 8.6 12 m
- 9.1 13 m
- - 25 m
- 0.02 100 nA
- 0.05 10 µA
- - 500 µA
- 55 - nC
- 13 - nC
- 28 - nC
- 19 -
- 114 -
- 250 -
- 216 -
ns
ns
ns
ns
- 3.5 - nH
- 7.5 - nH
- 3300 -
- 560 -
- 370 -
pF
pF
pF
October 1999
2
Rev 1.200


Part Number PSMN010-55D
Description N-channel logic level TrenchMOS transistor
Maker Philips
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