74HCT10 Datasheet | Philips Semiconductors

FEATURES - Output capability: standard - ICC category: SSI GENERAL DESCRIPTION 74HC/HCT10 The 74HC/HCT10 are high-speed Si-gate CMOS devices and are pin patible with low power Schottky TTL (LSTTL). They are specified in pliance with JEDEC standard no. 7A. The 74HC/HCT10 provide the 3-input NAND function. QUICK REFERENCE DATA GND = 0 V; Tamb = 25 °C; tr = tf = 6 ns TYPICAL SYMBOL t PHL/ t PLH CI CPD Notes 1. CPD is used to determine the dynamic power dissipation (PD in µW): PD = CPD × VCC2 × fi + ∑ (CL × VCC2 × f O) where: fi = input frequency in MHz fo = output frequency in MHz CL = output load capacitance in p F VCC = supply voltage in V ∑ (CL × VCC2 × fo) = sum of outputs 2. For HC the condition is VI = GND to VCC For HCT the condition is VI = GND to VCC - 1.5 V. ORDERING INFORMATION See “74HC/HCT/HCU/HCMOS Logic Package Information”. PARAMETER propagation delay n A, n B, n C to n Y input capacitance power dissipation capacitance per gate notes 1 and 2 CONDITIONS HC CL = 15 p F; VCC = 5 V 9 3.5 12 11 3.5 14 HCT ns p F p F UNIT December 1990 Philips Semiconductors Product specification Triple 3-input NAND gate PIN DESCRIPTION PIN NO. 1, 3, 9 2, 4, 10 13, 5, 11 12, 6, 8 7 14 SYMBOL 1A to 3A 1B to 3B 1C to 3C 1Y to 3Y GND VCC NAME AND FUNCTION data inputs data inputs data inputs data outputs ground (0 V) positive supply voltage 74HC/HCT10 Fig.1 Pin configuration. Fig.2 Logic symbol. Fig.3 IEC logic symbol. FUNCTION TABLE INPUTS n A L L L L H H H H Notes Fig.4 Functional diagram. Fig.5 Logic diagram (one gate). 1. H = HIGH voltage level L = LOW voltage level n B L L H H L L H H n C L H L H L H L H OUTPUT n Y H H H H H H H L December 1990 Philips Semiconductors Product specification Triple 3-input NAND gate DC CHARACTERISTICS FOR 74HC For the DC characteristics see “74HC/HCT/HCU/HCMOS Logic Family Specifications”. Output capability: standard ICC category: SSI AC CHARACTERISTICS FOR 74HC GND = 0 V; tr = tf = 6 ns; CL = 50 p F Tamb (°C) 74HC SYMBOL PARAMETER +25 min....