74HC5555 Datasheet | Philips Semiconductors

FEATURES - Positive and negative edge triggered - Retriggerable or non-retriggerable - Programmable delay minimum: 100 ns maximum: depends on input frequency and division ratio - Divide-by range of 2 to 224 - Direct reset terminates output pulse - Very low power consumption in triggered start mode - 3 oscillator operating modes: - RC oscillator - Crystal oscillator - External oscillator - Device is unaffected by variations in temperature and VCC when using an external oscillator - Automatic power-ON reset - Schmitt trigger action on both trigger inputs - Direct drive for a power transistor - Low power consumption in active mode with respect to TTL type timers - High precision due to digital timing - Output capability: 20 m A - ICC category: MSI. APPLICATIONS - Motor control - Attic fan timers - Delay circuits - Automotive applications - Precision timing - Domestic appliances. CI CPD Notes QUICK REFERENCE DATA GND = 0 V; Tamb = 25 °C; tr = tf = 6 ns. SYMBOL t PHL/t PLH PARAMETER propagation delay A, B to Q/Q MR to Q/Q RS to Q/Q input capacitance power dissipation capacitance per buffer GENERAL DESCRIPTION The 74HC/HCT5555 are high-speed Si-gate CMOS devices and are pin patible with low power Schottky TTL (LSTTL). They are specified in pliance with JEDEC standard no. 7A. The 74HC/HCT5555 are precision programmable delay timers which consist of: - 24-stage binary counter - integrated oscillator (using external timing ponents) 74HC/HCT5555 - retriggerable/non-retriggerable monostable - automatic power-ON reset - output control logic - oscillator control logic - overriding asynchronous master reset (MR). CONDITIONS CL = 15 p F; VCC = 5 V 24 19 26 TYP. 24 20 28 3.5 36 UNIT ns ns ns p F p F 3.5 notes 1 and 2 23 1. CPD is used to determine the dynamic power dissipation (PD in µW): PD = CPD x VCC2 x fi + Σ(CL x VCC2 x fo) where: fi = input frequency in MHz fo = output frequency in MHz Σ(CL x VCC2 x fo) = sum of outputs. CL = output load capacitance in p F VCC = supply...