74HC251 Datasheet | Philips Semiconductors

FEATURES - True and plement outputs - Both outputs are 3-state for further multiplexer expansion - Multifunction capability - Permits multiplexing from n-lines to one line - Output capability: standard - ICC category: MSI GENERAL DESCRIPTION The 74HC/HCT251 are high-speed Si-gate CMOS devices and are pin patible with low power Schottky TTL (LSTTL). They are specified in pliance with JEDEC standard no. 7A. QUICK REFERENCE DATA GND = 0 V; Tamb = 25 °C; tr = tf = 6 ns 74HC/HCT251 The 74HC/HCT251 are the logic implementations of single-pole 8-position switches with the state of three select inputs (S0, S1, S2) controlling the switch positions. Assertion (Y) and negation (Y) outputs are both provided. The output enable input (OE) is active LOW. The logic function provided at the output, when activated, is: Y = OE.(I0.S0.S1.S2 + I1.S0.S1.S2 + + I2.S0.S1.S2 + I3.S0.S1.S2 + + I4.S0.S1.S2 + I5.S0.S1.S2 + + I6.S0.S1.S2 + I7.S0.S1.S2) Both outputs are in the high impedance OFF-state (Z) when the output enable input is HIGH, allowing multiplexer expansion by tying the outputs. TYPICAL SYMBOL t PHL/ t PLH PARAMETER propagation delay In to Y In to Y Sn to Y Sn to Y CI CPD Notes 1. CPD is used to determine the dynamic power dissipation (PD in µW): PD = CPD × VCC2 × fi + ∑ (CL × VCC2 × fo) where: fi = input frequency in MHz fo = output frequency in MHz ∑ (CL × VCC2 × fo) = sum of outputs CL = output load capacitance in p F VCC = supply voltage in V 2. For HC the condition is VI = GND to VCC For HCT the condition is VI = GND to VCC - 1.5 V ORDERING INFORMATION See “74HC/HCT/HCU/HCMOS Logic Package Information”. input capacitance power dissipation capacitance per package notes 1 and 2 CONDITIONS HC CL = 15 p F; VCC = 5 V 15 17 20 21 3.5 44 19 19 20 21 3.5 46 ns ns ns ns p F p F HCT UNIT December 1990 Philips Semiconductors Product specification 8-input multiplexer; 3-state PIN DESCRIPTION PIN NO. 4, 3, 2, 1, 15, 14, 13, 12 5 6 7 8 11, 10, 9 16 SYMBOL I0 to I7 Y Y OE GND S0, S1, S2...