74F382 Datasheet | Philips Semiconductors

FEATURES - Performs six arithmetic and logic functions - Selectable Low (clear) and High (preset) functions - Low-input loading minimizes drive requirements - Carry output for ripple expansion - Overflow output for Two’s plement arithmetic DESCRIPTION The 74F382 performs three arithmetic and three logic operations on two 4-bit words, A and B. Two additional Select (S0- S2) input codes force the Function outputs Low or High. An overflow output is provided for convenience in Two’s plement arithmetic. A carry output is provided for ripple expansion. For high-speed expansion using a carry look-ahead generator, refer to the 74F381 data sheet. Signals applied to the Select inputs, S0- S2, determine the mode of operation, as indicated in the Function Select Table. An extensive listing of input and output levels is shown in the Function Table. The circuit performs the arithmetic functions for either active-HIgh or active-Low operands, with output levels in the same convention. In the subtract operating modes, it is necessary to force a carry (High for active-HIgh operands, Low for active-Low operands) into the Cn input of the least significant package. Ripple expansion is illustrated in Figure 1. The overflow output OVR is the Exclusive-OR of Cn+3 and Cn+4; a High signal on OVR indicates overflow in Two’s plement operation (See Table 2 for Two’s plement arithmetic). Typical delays for Figure 1 are given in Table 1. When the 74F382 is cascaded to handle word lengths longer than 4 bits, only the most significant overflow (OVR) output is used. PIN CONFIGURATION A1 1 B1 2 A0 3 B0 4 S0 5 S1 6 S2 7 F0 8 20 V CC 19 A2 18 B2 17 A3 16 B3 15 Cn 14 Cn+4 13 OVR 12 F3 11 F2 F1 9 GND 10 SF00935 TYPE 74F382 TYPICAL PROPAGATION DELAY 7.0ns TYPICAL SUPPLY CURRENT (TOTAL) 54m A ORDERING INFORMATION DESCRIPTION 20-pin plastic DIP 20-pin plastic SO MERCIAL RANGE VCC = 5V ±10%, Tamb = 0°C to +70°C N74F382N N74F382D PKG DWG # SOT146-1 SOT163-1 INPUT AND OUTPUT LOADING AND FAN OUT...