74F224 Datasheet | Philips Semiconductors

Philips Semiconductors FAST Products Preliminary specification 16 × 4 Synchronous FIFO (3-State) Features outputs - Independent synchronous inputs and - Organized as 16 words of 4 bits - DC to 50MHz data rate - 3-State outputs - Cascadable in word- width and depth direction TYPICAL SUPPLY CURRENT (TOTAL) 90m A DESCRIPTION This 64-bit active element First-In-First-Out (FIFO) is a monolithic Schottky-clamped transistor-transistor logic (STLL) array organized as 16 words of 4-bits each. A memory system using the 74F224 can be easily expanded in multiples of 15m+1 words or of 4n bits, or both (where n is the number of packages in the horizontal array). However, an external gating is required (see Figure 1). For longer words using 74F224, the IR signals of the first-rank packages and OR signals of the last-rank packages must be ANDed for proper synchronization.The 3-State outputs controlled by a single input (OE) make bus connection and multiplexing easy. TYPE TYPICAL fmax 50MHz ORDERING INFORMATION ORDER CODE DESCRIPTION MERCIAL RANGE VCC = 5V ±10%, Tamb = 0°C to +70°C 16-pin plastic Dual In-line Package 16-pin plastic Small Outline Large N74F224N N74F224D 0406C 0171B DRAWING NUMBER INPUT AND OUTPUT LOADING AND FAN OUT TABLE PINS LDCP D0 - D3 OE UNCP MR IR Q0 - Q3 Load clock input Data inputs Output enable input (active high) Unload clock input Master reset input (active low) Input ready output Data outputs DESCRIPTION 74F (U.L.) HIGH/LOW 1.0/1.0 1.0/1.0 1.0/1.0 1.0/1.0 1.0/1.0 50/33 50/33 50/33 LOAD VALUE HIGH/LOW 20µA/0.6m A 20µA/0.6m A 20µA/0.6m A 20µA/0.6m A 20µA/0.6m A 1.0m A/20m A 1.0m A/20m A 1.0m A/20m A OR Output ready output NOTE TO INPUT AND OUTPUT LOADING AND FAN OUT TABLE 1. One (1.0) FAST unit load is defined as: 20µA in the high state and 0.6m A in the low state. PIN CONFIGURATION LOGIC SYMBOL 4 5 6 7 IED/IEEE SYMBOL FIFO 16 X 4 1 9 EN5 CT=0 CT<0 CTR & +/C1 Z2 CT>0 15 4 1D 5 & - CT=0 2 & V4 4,5 13 12 13 10 2 3 2 14 OE 1 IR 2 16 15...