PLL520-89 Datasheet PDF ((PLL520-8x) Low Phase Noise VCXO) | Download PhaseLink Corporation PLL520-89

PLL520-89 - (PLL520-8x) Low Phase Noise VCXO

This page provides the datasheet information for the PLL520-89, a member of the PLL520-88 (PLL520-8x) Low Phase Noise VCXO family.

Description

The PLL520-88 (PECL) and PLL520-89 (LVDS) are VCXO ICs specifically designed to work with fundamental crystals between 19MHz and 65MHz.

The selectable divide by two feature extends the operation range from 9.5MHz to 65MHz.

Features

19MHz to 65MHz fundamental crystal input. Output range: 9.5MHz.
65MHz Complementary outputs: PECL or LVDS output. Selectable OE Logic (enable high or enable low). Integrated variable capacitors. Supports 2.5V or 3.3V Power Supply. Available in 16 pin TSSOP package. VDD XIN XOUT DNC S2 OE 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 DNC DNC GNDBUF QBAR VDDBUF Q GNDBUF GND PLL 520-8x.

Datasheet Details

Part number	PLL520-89
Manufacturer	PhaseLink Corporation
File Size	250.87 KB
Description	(PLL520-8x) Low Phase Noise VCXO
Datasheet	PLL520-89 Datasheet
Additional preview pages of the PLL520-89 datasheet.

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Full PDF Text Transcription

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Preliminary www.DataSheet4U.com PLL520-88/-89 Low Phase Noise VCXO (9.5-65MHz) PIN CONFIGURATION FEATURES • • • • • • • 19MHz to 65MHz fundamental crystal input. Output range: 9.5MHz – 65MHz Complementary outputs: PECL or LVDS output. Selectable OE Logic (enable high or enable low). Integrated variable capacitors. Supports 2.5V or 3.3V Power Supply. Available in 16 pin TSSOP package. VDD XIN XOUT DNC S2 OE 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 DNC DNC GNDBUF QBAR VDDBUF Q GNDBUF GND PLL 520-8x DESCRIPTION The PLL520-88 (PECL) and PLL520-89 (LVDS) are VCXO ICs specifically designed to work with fundamental crystals between 19MHz and 65MHz. The selectable divide by two feature extends the operation range from 9.5MHz to 65MHz.

Published: Feb 6, 2009 |