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PhaseLink Corporation

PLL520-39 Datasheet Preview

PLL520-39 Datasheet

(PLL520-3x) PECL and LVDS Low Phase Noise VCXO

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PLL520-38/-39
w w wP. DEaCt aLS hae entd4 UL. cVo mDS Low Phase Noise VCXO (for 65-130MHz Fund Xtal)
FEATURES
65MHz to 130MHz Fundamental Mode Crystal.
Output range: 65MHz – 130MHz (no PLL).
Low Injection Power for crystal 50uW.
PECL (PLL520-38) or LVDS output (PLL520-39).
Integrated variable capacitors.
Supports 2.5V or 3.3V-Power Supply.
Available in 16-Pin (TSSOP or 3x3 QFN).
DESCRIPTION
The PLL520-38/-39 is a family of VCXO IC’s
specifically designed to pull high frequency
fundamental crystals from 65MHz to 130MHz, with
selectable PECL or LVDS outputs.. They achieve
very low current into the crystal resulting in better
overall stability. Their internal varicaps allow an on
chip frequency pulling, controlled by the VCON
input. Their very low jitter makes them ideal for the
most demanding timing requirements.
BLOCK DIAGRAM
PIN CONFIGURATION
VDD
XIN
XOUT
N/C
N/C
OE
VCON
GND
1
2
3
4
5
6
7
8
16 N/C
15 N/C
14 GND
13 CLKC
12 VDD
11 CLKT
10 N/C
9 N/C
XIN
XOUT
N/C
OE
12 11 10 9
13 8
14 7
P520-3x
15 6
16 5
1234
GND
CLKC
VDD
CLKT
VCON Oscillator
Amplifier
XIN
w/
integrated
varicaps
XOUT
OE
Q
Q
PLL520-38/-39
OUTPUT ENABLE LOGICAL LEVELS
Part #
PLL520-38
PLL520-39
OE
0
(Default)
1
0
1
(Default)
State
Output enabled
Tri-state
Tri-state
Output enabled
OE input: Logical states defined by PECL levels for PLL520-38
Logical states defined by CMOS levels for PLL520-39
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 09/20/04 Page 1




PhaseLink Corporation

PLL520-39 Datasheet Preview

PLL520-39 Datasheet

(PLL520-3x) PECL and LVDS Low Phase Noise VCXO

No Preview Available !

PLL520-38/-39
wwwP.DaEtaCSheLet4aU.ncodm LVDS Low Phase Noise VCXO (for 65-130MHz Fund Xtal)
PIN DESCRIPTIONS
Name
XIN
XOUT
OE
VCON
GND
CLKT
CLKC
N/C
VDD
Number
2
3
6
7
8, 14
11
13
4,5,9,10,15,16
1, 12
Type
I
I
I
I
P
O
O
-
P
Description
Crystal input. See Crystal Specifications on page 2.
Crystal output. See Crystal Specifications on page 2.
Output enable. See Output Enable Logic table on page 1.
Voltage control input.
Ground.
True output PECL (PLL520-38) or LVDS (PLL520-39).
Complementary output PECL (PLL520-38) or LVDS (PLL520-39).
Not connected.
Power supply.
ELECTRICAL SPECIFICATIONS
1. Absolute Maximum Ratings
PARAMETERS
SYMBOL
MIN.
MAX.
UNITS
Supply Voltage
Input Voltage, dc
Output Voltage, dc
Storage Temperature
Ambient Operating Temperature*
Junction Temperature
Lead Temperature (soldering, 10s)
ESD Protection, Human Body Model
VDD 4.6 V
VI
-0.5 VDD+0.5
V
VO
-0.5 VDD+0.5
V
TS -65 150 °C
TA -40 85 °C
TJ 125 °C
260 °C
2 kV
Exposure of the device under conditions beyond the limits specified by Maximum Ratings for extended periods may cause permanent damage to the
device and affect product reliability. These conditions represent a stress rating only, and functional operations of the device at these or any other
conditions above the operational limits noted in this specification is not implied.
* Note: Operating Temperature is guaranteed by design for all parts (COMMERCIAL and INDUSTRIAL), but tested for COMMERCIAL grade only.
2. Crystal Specifications
PARAMETERS
Built-in Capacitance
Inter-electrode capacitance
C0/C1 ratio (gamma)
Oscillation Frequency
SYMBOL
CX+
CX-
C0
γ
OF
CONDITIONS
65MHz to 130MHz
(VDD=3.3V)
Fund.
MIN. TYP.
2.6
65
MAX.
2
2
UNITS
pF
300 -
130 MHz
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 09/20/04 Page 2


Part Number PLL520-39
Description (PLL520-3x) PECL and LVDS Low Phase Noise VCXO
Maker PhaseLink Corporation
Total Page 7 Pages
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