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PhaseLink Corporation

PLL130-69 Datasheet Preview

PLL130-69 Datasheet

(PLL130-68/-69) High Speed Translator Buffers

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PLL130-68/-69
High Speed Translator Buffers: Single ended to PECL or LVDS
FEATURES
Differential PECL (PLL130-68) or LVDS
(PLL130-69) output.
Accepts any single-ended REFIN input (with
as low as 100mV swing).
Internal AC coupling of REFIN
Input range from 1.0MHz to 1.0 GHz.
No Vref required.
www.DataSheet4U.Ncoomexternal current source required.
2.5 to 3.3V operation.
Available in 3x3mm QFN.
PIN CONFIGURATION
(TOP VIEW)
NC
REFIN
NC
NC
16 15 14
1
13
12
2 PLL130-6x 11
3 10
45 6 7 8 9
NC
Q
Q_bar
OESEL
DESCRIPTION
The PLL130-68 and PLL130-69 are low cost,
high performance, high speed, translator buffers
that reproduce any input frequency from DC to
1.0GHz. They provide a pair of differential out-
puts (PECL for PLL130-68 or LVDS for PLL130-
69). Thanks to an internal AC coupling of the
reference input (REFIN), any input signal with at
least 100mV swing can be used as reference
signal, regardless of its DC value. These chips
are ideal for conversion from clipped sine wave,
TTL, CMOS, or differential signal to LVDS or
PECL.
BLOCK DIAGRAM
OUTPUT ENABLE LOGICAL LEVELS
PLL130-68
OESEL
0 (Default)
1
OECTRL
0 (Default)
1
0
1 (Default)
OUTPUT STATE
Output enabled
Tri-state
Tri-state
Output enabled
OECTRL input: Logical states defined by PECL levels.
PLL130-69
OESEL
0 (Default)
1
OECTRL
0
1 (Default)
0 (Default)
1
OUTPUT STATE
Tri-state
Output enabled
Output enabled
Tri-state
OECTRL input: Logical states defined by CMOS levels.
REFIN
AC
Coupling
Input
Amplifier
Q_BAR
Q
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 09/09/04 Page 1




PhaseLink Corporation

PLL130-69 Datasheet Preview

PLL130-69 Datasheet

(PLL130-68/-69) High Speed Translator Buffers

No Preview Available !

PLL130-68/-69
High Speed Translator Buffers: Single ended to PECL or LVDS
PIN DESCRIPTION
Name
NC
REFIN
OECTRL
GND
www.DataSheet4UO.cEoSmEL
Q_BAR
Q
VDD
Q
Q_BAR
Pin number
1, 3, 4, 6,
8, 12, 14
2
5
7
9
10
11
13
15
16
Type
-
I
I
P
I
O
O
P
O
O
Description
No connection.
Reference input signal. The frequency of this signal will be reproduced
at the output (after translation to PECL or LVDS level).
Output enable input (See OE Logic Table on page 1).
Ground connector.
Output enable logic selector (See OE Logic Table on page 1).
Complementary output. PECL_bar on PLL130-68, LVDS_bar on
PLL130-69.
True output. PECL on PLL130-68, LVDS on PLL130-69.
3.3V Power supply.
Additional true output. PECL on PLL130-68, LVDS on PLL130-69. This
output is the same as pin 11.
Additional complementary output. PECL_bar on PLL130-68, LVDS_bar
on PLL130-69. This output is the same as pin 10.
ELECTRICAL SPECIFICATIONS
1. Absolute Maximum Ratings
PARAMETERS
SYMBOL
MIN.
MAX.
UNITS
Supply Voltage
Input Voltage, dc
Output Voltage, dc
Storage Temperature
Ambient Operating Temperature*
Junction Temperature
Lead Temperature (soldering, 10s)
ESD Protection, Human Body Model
VDD 4.6 V
VI
-0.5 VDD+0.5
V
VO
-0.5 VDD+0.5
V
TS -65 150 °C
TA -40 85 °C
TJ 125 °C
260 °C
2 kV
Exposure of the device under conditions beyond the limits specified by Maximum Ratings for extended periods may cause permanent damage to the
device and affect product reliability. These conditions represent a stress rating only, and functional operations of the device at these or any other con-
ditions above the operational limits noted in this specification is not implied.
* Note: Operating Temperature is guaranteed by design for all parts (COMMERCIAL and INDUSTRIAL), but tested for COMMERCIAL grade only.
2. General Electrical Specifications
PARAMETERS
Supply Current
(both outputs loaded)
Operating Voltage
Output Clock Duty Cycle
Short Circuit Current
SYMBOL
IDD
VDD
CONDITIONS
Fout = 156.25MHz, PECL
Fout = 156.25MHz, LVDS
@ Vdd – 1.3V (PECL)
@ 1.25V (LVDS)
MIN. TYP. MAX.
45 48
51
22 25
28
2.97 3.63
Same as input
Same as input
±50
UNITS
mA
V
%
mA
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 11/29/04 Page 2


Part Number PLL130-69
Description (PLL130-68/-69) High Speed Translator Buffers
Maker PhaseLink Corporation
Total Page 5 Pages
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